1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas of drain and source regions are connected to the metallization system of the semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain and a source.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, memory devices and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor elements but the electrical performance of the complex wiring fabric, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the individual circuit elements and of the various stacked metallization layers.
Furthermore, in order to establish a connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided, which connects to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and to a respective metal line in the metallization layer. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level may have to be provided with appropriate critical dimensions in the same order of magnitude. The contact elements may typically represent plugs which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, the interlayer dielectric material may be formed first and may be patterned so as to receive contact openings, which may extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. For this purpose, openings of very different depth may have to be formed in the interlayer dielectric material in order to connect to gate electrode structures or any other conductive lines formed above the semiconductor layer, while other contact openings have to extend down to a semiconductor layer, i.e., any contact areas formed therein. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions may be 100 nm and less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy, while the difference in etch depth may additionally contribute to the overall complexity of the patterning process.
After exposing the contact areas, which are frequently provided in the form of metal silicide regions, the contact metal, such as tungsten and the like, is deposited in the contact openings of different depth, thereby also contributing to a highly complex manufacturing process. For example, a plurality of contact openings are typically provided in the interlayer dielectric material so as to connect to the drain and source regions of transistors, wherein these contact openings may typically have a substantially round or square-like shape. Consequently, after providing the contact elements, the overall series resistance in the transistor, i.e., the resistance of the conductive path from one contact element through the source region, the channel region, the drain region and into the other contact element, may significantly depend on the resistivity for connecting to the contact areas, such as metal silicide regions provided in the drain and source areas. Upon further scaling of device dimensions, the contact resistivity for connecting to the drain and source areas of sophisticated transistor elements may represent a limiting factor of the overall transistor performance, thereby offsetting or al least reducing some of the advantages obtained by generally reducing the overall transistor dimensions. For example, in sophisticated manufacturing strategies, extremely complex mechanisms may be incorporated, such as strain-inducing semiconductor materials for enhancing charge carrier mobility in the channel region of the transistors, providing sophisticated gate electrode structures including high-k dielectric materials in combination with electrode metals and the like, which may per se result in superior transistor performance. For this purpose, superior contact regimes may also be required for efficiently connecting to the drain and source areas. In this context, it has been proposed to provide contact elements of increased lateral dimension along the transistor width direction to reduce the contact resistivity between the actual contact elements and the contact areas of the drain and source regions, such as the metal silicide regions. To this end, appropriate contact trenches may be formed in the interlayer dielectric material, which may subsequently be filled by an appropriate contact metal, thereby reducing the overall contact resistivity. On the other hand, providing contact trenches in the interlayer dielectric material so as to connect to the drain and source areas may significantly increase the fringing capacitance, which is to be understood as the parasitic capacitance between the gate electrode structures and the contact elements, thereby negatively affecting the overall AC performance of the transistor.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.